Clock-skew constrained cell placement

We present a quadratic programming based placement method for cell based designs. The approach is performance oriented and addresses constraints like area, timing, and clock-skew. While area and timing has been addressed in quite a few recent studies, clock skew is being addressed in this paper for the first time. These an quite important issues in VLSI design as it is always desirable to optimize and realize as many constraints early on in the design cycle. This also provides tight integration with high level synthesis based designs. The quadratic programming based placement incorporates mechanisms for incorporating many constraints. The method has been experimentally tested on several medium sized benchmarks. It has resulted in layouts which on comparable or better than tools like TimberWolf in a time that is a small fraction of TimberWolf