Hierarchical thermal modeling for SOI technology

The thermal environment in VLSI circuits is characterized by the existence of both small and isolated heat sources near the channel region and a vast volume (e.g. substrate) serving as the heat conduction media. The presence of a buried oxide layer in Silicon on Insulator technology introduces an additional thermal barrier between the device and Si substrate. The modeling and simulation of such situations are usually handled with either element-based simulations (e.g. finite element methods, lumped element methods) or direct methods based on integral transform. In practice neither approach can maintain both accuracy and efficiency at the same time. We have developed a new methodology for the simulation of the thermal behavior of high-density integrated circuits at various levels of complexity. It treats the structured thermal conduction media hierarchically and thus is capable of relating thermal behaviors over a wide range of length scales. As a demonstration this methodology is applied to model heat conduction and self heating effects in SOI technology. Compared to the traditional element-based numerical method used to solve the Laplace equation, out method greatly reduces the number of nodes and the computing time while maintaining accuracy.