An efficient test generation technique for sequential circuits with repetitive sub-circuits

An efficient hierarchical testing algorithm for sequential circuits with repetitive sub-circuits has been proposed and implemented. This algorithm uses the bus fault model which helps in significant reduction of modeled circuit components and faults. The algorithm is significantly faster than conventional gate-level test generators for a class of sequential circuits since it attempts to generate test vectors in parallel. The algorithm resolves high-level incompatibility encountered during test generation whenever it is possible. This is done by unfolding the high-level model of the circuit and obtaining a loop in the corresponding state transition graph