DocumentCode
3276970
Title
RFICs packages electrical performance comparison of both ULTRA-CSP and Standard TSOP
Author
Hsu, Terry ; Chiang, Kevin ; Wang, Yu-Po
Author_Institution
Siliconware Precision Industries Co. Ltd., Taichung, Taiwan
fYear
2002
fDate
10-12 Dec. 2002
Firstpage
25
Lastpage
31
Abstract
The requirement for low cost, small size and high density for high-speed system drives the design of packages to smaller package size. ULTRA CSP is an advanced technology to meet the above targets. ULTRA CSP is a wafer level package developed by FCT. Under high frequency operation, the parasitics associated with the package will significantly degrade the package performance. An unsuitable package may cause resonance, coupling, impedance mismatch and frequency dependent loss. So, providing accurate package parasitics is critical to the success of the system design. In this paper, the electrical model of ULTRA CSP has been established based on the S-parameter simulation. When compared with the TSOP package, ULTRA-CSP shows smaller parasitics in the equivalent model. This paper also compares the performance of the ULTRA-CSP and Standard TSOP from the view point of propagation delay, crosstalk noise, insertion loss, return loss and maximum allowable working frequency. Based on the analysis result, is provided the package layout guideline for designer reference.
Keywords
S-parameters; chip scale packaging; crosstalk; delays; equivalent circuits; frequency-domain analysis; integrated circuit noise; integrated circuit packaging; losses; radiofrequency integrated circuits; time-domain analysis; RFIC packages; S-parameter simulation; Standard TSOP; ULTRA-CSP; crosstalk noise; electrical model; electrical performance comparison; high frequency operation; insertion loss; maximum allowable working frequency; package parasitics; propagation delay; return loss; wafer level package; wideband equivalent circuit model; Chip scale packaging; Costs; Degradation; Frequency; Impedance; Insertion loss; Propagation losses; Radiofrequency integrated circuits; Resonance; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2002. 4th
Print_ISBN
0-7803-7435-5
Type
conf
DOI
10.1109/EPTC.2002.1185591
Filename
1185591
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