Title :
Synthesis of testable pipelined datapaths using genetic search
Author :
Ravikumar, C.P. ; Saxena, V.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
Abstract :
In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to explore a 3D search space, the three dimensions being the chip area, average latency, and the testability of the datapath. Testability of a design is evaluated by counting the number of self-loops in the structure graph of the data path. Each design is characterized by a four-tuple consisting of (i) the latency and schedule information, (ii) the module allocation, (iii) operation-to-module binding, and (iv) value-to-register binding. An initial population of designs is constructed from the given data flow graph using different latency cycles whose average latency is in the specified range. Multiple scheduling heuristics are used to generate schedules for the DFG. For each of the resulting scheduled data flow graphs, we decide on an allocation of modules and registers based on a lower bound estimated using the schedule and latency information. The operation-to-module binding and the value-to-register binding are then carried out. A fitness measure is evaluated for each of the resulting data paths; this fitness measure includes one component for each of the three search dimensions. We have implemented TOGAPS on a Sun/SPARC 10 and studied its performance on a number of benchmark examples. Results indicate that TOGAPS finds area-optimal datapaths for the specified latency cycle, while reducing the number of self-loops in the data path
Keywords :
data flow graphs; design for testability; genetic algorithms; high level synthesis; pipeline processing; search problems; TOGAPS; Testability-Oriented Genetic Algorithm for Pipeline Synthesis; area-optimal datapath; data flow graph; fitness measure; four-tuple; genetic search; latency; module allocation; multiple scheduling heuristic; operation-to-module binding; register-level model; self-loop; synthesis; testable pipelined datapath; three-dimensional search space; value-to-register binding; Algorithm design and analysis; Automatic testing; Delay; Flow graphs; Genetic algorithms; Logic testing; Pattern analysis; Pipelines; Sun; Test pattern generators;
Conference_Titel :
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7228-5
DOI :
10.1109/ICVD.1996.489485