Clocked semi-floating-gate ultra low-voltage inverting current mirror

In this paper we present a low voltage inverting current mirror based on clocked semi-floating-gate transistors used in low-voltage digital CMOS circuits. By applying offsets to semi-floating-gate nodes the current level may be increased compared to non-floating-gate design applying ultra low supply voltages. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed inverted current mirror can operate at supply voltages below 250 mV. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.