Bipartitioning for hybrid FPGA-software simulation

Simulation is an important step in the design cycle of VLSI systems. The increasing size and complexity of modern systems require simulation techniques optimized for time. Researchers are resorting to parallel simulation to reduce simulation time. Logic partitioning plays an important role in parallel simulation. Two factors, concurrency amongst the partitions and communication between them, determine the effectiveness of partitioning. The concurrency achieved and the communication overhead resulting from the intersecting signals can directly affect the speed-up achieved in the simulation. Hybrid FPGA-software simulation offers an alternative for increasing the speed of simulation. In addition to above factors, size and cost of FPGA also determine the partitioning technique for FPGA based emulation. This paper addresses the issues involved in hybrid FPGA-software simulation and presents a new partitioning scheme. With our approach, communication between partitions reduces to at least 50% of that observed in the best of the other algorithms. Also for most of the benchmarks, only 25% of the circuit elements are in the FPGA partition. Presimulation is employed as an effective tool to achieve this aim