• DocumentCode
    3277457
  • Title

    Low-power multiplier design with row and column bypassing

  • Author

    Yan, Jin-Tai ; Chen, Zhi-Wei

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Chung-Hua Univ., Hsinchu, Taiwan
  • fYear
    2009
  • fDate
    9-11 Sept. 2009
  • Firstpage
    227
  • Lastpage
    230
  • Abstract
    Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multipliers and the 2D bypass multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% of the power dissipation with only 15% hardware overhead on the average for 4 × 4, 8 × 8 and 16 × 16 multipliers.
  • Keywords
    adders; integrated circuit design; logic design; low-power electronics; multiplying circuits; 2D bypass multiplier; column-bypassing multiplier; half adder; hardware overhead; incremental adder; low-power multiplier design; power dissipation; row-bypassing multiplier; Adders; Birth disorders; Capacitance; Clocks; Computer science; Design engineering; Digital signal processing; Hardware; Power dissipation; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference, 2009. SOCC 2009. IEEE International
  • Conference_Location
    Belfast
  • Print_ISBN
    978-1-4244-4940-8
  • Electronic_ISBN
    978-1-4244-4941-5
  • Type

    conf

  • DOI
    10.1109/SOCCON.2009.5398054
  • Filename
    5398054
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3277457