Title :
A novel low power, variable resolution pipelined ADC
Author :
Kumar, Mahesh ; Veeramachaneni, Sreehari ; Srinivas, M.B.
Author_Institution :
Int. Inst. of Inf. Technol., Hyderabad, India
Abstract :
In this paper, a novel low power, variable resolution pipelined analog to digital converter (ADC) with an embedded sample and hold (S/H) circuit is presented. The ADC circuit uses a peak detector to make the resolution variable. It is capable of operating up to a sampling frequency of 200MSPS at 8-bit, 10-bit, and 12-bit resolution with a supply voltage of 2.5 V. The proposed design has DNL< ±0.25LSB, INL< ±0.5LSB, SNR of 71.5 dB and SNDR of 69.1 dB with a peak power consumption of 24 mW. The ADC is designed in thick gate process and its performance is verified in post layout simulations at 65nm technology node.
Keywords :
analogue-digital conversion; integrated circuit design; low-power electronics; sample and hold circuits; analog to digital converter; low-power ADC; power 24 mW; sample and hold circuit; size 65 nm; variable resolution pipelined ADC; voltage 2.5 V; Capacitors; Circuits; Detectors; Diodes; Photonic band gap; Regulators; Sampling methods; Signal resolution; Virtual colonoscopy; Voltage;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398061
