Title :
A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS
Author :
Lee, Seungwon ; Kim, Tae-Ho ; Yoo, Jae-Wook ; Kang, Jin-Ku
Author_Institution :
Dept. of Electron. Eng., INHA Univ., Incheon, South Korea
Abstract :
This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.
Keywords :
CMOS digital integrated circuits; clocks; voltage-controlled oscillators; CMOS process; DisplayPort standard; VCO; bit rate 1.62 Gbit/s; bit rate 2.7 Gbit/s; clock and data recovery circuit; dual mode voltage-controlled oscillator; mode switch control; peak-to-peak jitters; power 80 mW; size 0.18 μm; voltage 1.8 V; CMOS process; Circuits; Clocks; Frequency; Jitter; Power dissipation; Semiconductor device measurement; Switches; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398064
