Handel-C Implementation of Early-Access Partial-Reconfiguration for Software Defined Radio

The new Xilinx Early-Access Partial-Reconfiguration (EAPR) FPGA technology exhibits a clear advantage over the former modular-based partial-reconfiguration flow. This paper compares a Handel-C implementation of the two approaches, demonstrating the limitations of the old method, which are fully addressed by the EAPR. It is argued here that the combination of Handel-C and EAPR offers a viable approach towards realization of the future Software Defined Radio (SDR) systems. Two EAPR-based SDR architectures are presented, which trade off complexity for reconfiguration speed. Finally a cost-efficient, fast mode-switching architecture, particularly suitable for Time Division Duplex (TDD) radio systems is presented. The proposed architecture utilizes this property to dynamically reconfigure the transmission and reception chain algorithms at different times.