SOPC Builder, a Novel Design Methodology for IP Integration

The International Technology Roadmap for Semiconductors (ITRS) estimates that 30% of project development costs are attributed to design integration. Conventionally, this need is met by the application of industry standards to design tools, IP and design methodologies. With the numerous IP interface standards today, IP developers have accepted that a "gasketO can be used to wrap the "nativeO interface of the IP core with the appropriate bus interface but even with this approach, IP integration still remains a significant portion of the design effort. Systems are defined by their components but rarely does the interconnect structure add sufficient value or it to be described in the product literature. While the interconnect logic is a necessity, the time spent to create such logic should be minimized. Development tools such as SOPC (System-On-A-Programmable-Chip) Builder can save valuable development time by efficiently generating the interconnect logic required.