A flow regulator for On-Chip Communication

Author

Lu, Zhonghai ; Brachos, Dimitris ; Jantsch, Axel

Author_Institution

KTH - The R. Inst. of Technol., Stockholm, Sweden

fYear

2009

fDate

9-11 Sept. 2009

Firstpage

151

Lastpage

154

Abstract

We have proposed (Â¿, Â¿)-based flow regulation as a design instrument for system-on-chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where Â¿ bounds the traffic burstiness and Â¿ the traffic rate. In this paper, we present a hardware implementation of the regulator. We discuss its microarchitecture. Based on this microarchitecture, we design, implement and synthesize a multi-flow regulator for AXI. Our experiments show the effectiveness of such a regulation device on the control of delay, jitter and buffer requirements.

Keywords

delays; jitter; quality of service; system-on-chip; buffer requirement; cost-effective communication; delay control; flow regulation; jitter; microarchitecture; multiflow regulator; on-chip communication; quality-of-service; regulation device; system-on-chip; traffic burstiness; traffic rate; Communication system traffic control; Control system synthesis; Control systems; Delay effects; Hardware; Instruments; Microarchitecture; Quality of service; Regulators; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2009. SOCC 2009. IEEE International

Conference_Location

Belfast

Print_ISBN

978-1-4244-4940-8

Electronic_ISBN

978-1-4244-4941-5

Type

conf

DOI

10.1109/SOCCON.2009.5398072

Filename

5398072