• DocumentCode
    3277878
  • Title

    When does Network-on-Chip bypassing make sense?

  • Author

    Hollis, Simon J. ; Jackson, Chris

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK
  • fYear
    2009
  • fDate
    9-11 Sept. 2009
  • Firstpage
    143
  • Lastpage
    146
  • Abstract
    Networks-on-Chip (NoCs) are becoming widespread in contemporary multi-core and many-core designs. Amongst their appeals are regularity of layout and flexibility of topology. However, the energy consumed by routing nodes is now vastly more than that of an ALU operation in one of the processing cores they service. We present an evaluation of bypassing, a technique where selected traffic can avoid the full routing functionality of selected nodes in a NoC. When implemented correctly, bypassing can dramatically reduce the overall energy consumption of data flowing through the network. We address the questions of when bypassing should be deployed at a given node, how much energy will be saved by doing so, and present some equations to quantify and answer these questions. We show that if 74-80% of data, depending on router implementation, is destined for a node further away than that employing bypassing, then bypassing is energy-effective. Using these figures, we define guidelines for the use of bypassing for a wide variety of NoC designs.
  • Keywords
    integrated circuit design; network-on-chip; bypassing technique; network-on-chip; router; Computer science; Energy consumption; Energy efficiency; Logic; Network topology; Network-on-a-chip; Routing; Strontium; Switches; System recovery;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference, 2009. SOCC 2009. IEEE International
  • Conference_Location
    Belfast
  • Print_ISBN
    978-1-4244-4940-8
  • Electronic_ISBN
    978-1-4244-4941-5
  • Type

    conf

  • DOI
    10.1109/SOCCON.2009.5398074
  • Filename
    5398074