• DocumentCode
    3278045
  • Title

    A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm

  • Author

    Chang, Yi-Ming ; Chang, Ming-Hung ; Hwang, Wei

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
  • fYear
    2009
  • fDate
    9-11 Sept. 2009
  • Firstpage
    115
  • Lastpage
    118
  • Abstract
    This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range of the ADMDLL, we proposed the self-estimated successive approximation register-controlled (SESAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. By using the stack effect, the proposed leakage-reduced delay unit can save 12% leakage power consumption. After locking, the dynamic frequency monitor window is proposed to compensation phase error caused by PVT variations. The proposed ADMDLL is capable of operating in wide supply voltage range from 0.3V to 1.0V. The power dissipation is only 520¿W at 1.25GHz/1.0V, and 2.1 ¿W at 13MHz/0.3V, respectively. This work is based on UMC 90nm standard CMOS technology.
  • Keywords
    CMOS digital integrated circuits; delay lines; delay lock loops; integrated circuit design; PVT variations; SESAR algorithm; all-digital multiphase delay-locked loop; circuit area; compensation phase error; delay line; dynamic frequency monitor window; frequency 1.25 GHz; frequency 13 MHz; frequency-estimation selector; harmonic lock; leakage-reduced delay unit; micro-power applications; power 2.1 muW; power 520 muW; power dissipation; self-estimated SAR algorithm; self-estimated successive approximation register-controlled algorithm; size 90 nm; stack effect; standard CMOS technology; voltage 0.3 V to 1 V; wide locking range multiphase DLL; Approximation algorithms; CMOS technology; Circuits; Delay effects; Delay lines; Energy consumption; Frequency; Monitoring; Power dissipation; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference, 2009. SOCC 2009. IEEE International
  • Conference_Location
    Belfast
  • Print_ISBN
    978-1-4244-4940-8
  • Electronic_ISBN
    978-1-4244-4941-5
  • Type

    conf

  • DOI
    10.1109/SOCCON.2009.5398082
  • Filename
    5398082