Title :
Asymmetrical Write-assist for single-ended SRAM operation
Author :
Lin, Jihi-Yu ; Tu, Ming-Hsien ; Tsai, Ming-Chien ; Jou, Shyh-Jye ; Chuang, Ching-Te
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, asymmetrical write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8T SRAM cell. A 4 Kbit SRAM implemented in 90 nm CMOS technology achieves 1 uW/bit average power consumption at 6 MHz, Vmin of 410 mV at 6 MHz, and 234 MHz maximum operation frequency at 600 mV.
Keywords :
CMOS memory circuits; SRAM chips; circuit feedback; asymmetrical write-assist; cell virtual ground biasing; frequency 6 MHz; operation speed; positive feedback sensing; read static noise margin; single-ended SRAM operation; size 90 nm; storage capacity 4 Kbit; voltage 410 mV; voltage 600 mV; write margin; CMOS technology; Energy consumption; Feedback; Frequency; Inverters; Low voltage; MOS devices; Random access memory; System performance; Threshold voltage;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398086
