Title :
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor
Author :
Chouliaras, V.A. ; Manolopoulos, K. ; Reisis, D.
Author_Institution :
Dept. of Electron. & Electr. Eng., Loughborough Univ., Loughborough, UK
Abstract :
The efficiency of fused multiply add units plays a key role in the processor´s performance for a variety of applications. A design keeping the advantages of the FMA regarding the latency and the hardware utilization and also improving the result´s accuracy in both normalized and denormalized numbers is the subject of this work. The FMA unit has configurable latency and it is integrated in a VLIW processor. The VLSI TSMC 0.13 implementation achieved an operating frequency of 232.6 MHz and a final post-routed area of 121900.478 um2.
Keywords :
VLSI; floating point arithmetic; multiplying circuits; multiprocessing systems; VLIW processor; VLSI TSMC; configurable length; frequency 232.6 MHz; fused multiply-add floating point unit; post-routed area; Application software; Delay; Frequency; Hardware; Laboratories; Physics; Pipelines; Registers; VLIW; Very large scale integration;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398088
