DocumentCode
3278195
Title
ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs
Author
Forsell, M.
Author_Institution
VTT Electron., Oulu
fYear
2005
fDate
17-17 Nov. 2005
Firstpage
90
Lastpage
95
Abstract
Programming and design skills in parallel computing related to systems on chip (SOC) will become increasingly important since future SOCs will have multiple processors interconnected via on-chip networks (NOC). Unfortunately there exist no easy-to-use tools for learning and experimenting with multiprocessor (MP)SOCs/NOCs, but one must use ad-hoc combinations of tools, methodologies and sample applications from very different sources. In this paper we introduce a parallel computing learning set (Parle) for configurable shared memory MPSOCs/NOCs and corresponding theoretical parallel random access machines (PRAM). The learning set consists of an experimental optimizing compiler for high-level parallel programming language e and assembler, linker, loader, simulator with a graphical user interface and statistical tools, and sample e/assembler code. Using the set, a student/designer can easily ivrite simple parallel programs, compile and load them into a configurable MPSOC/NOC platform, execute/debug them, gather statistics and explore the performance, utilization, and gate count estimations with different architectural parameters. The learning set runs on Mac OS X systems and is available for non-profit educational purposes.
Keywords
circuit analysis computing; computer aided instruction; graphical user interfaces; multiprocessor interconnection networks; network-on-chip; optimising compilers; parallel programming; program assemblers; program debugging; MPSOCs/NOCs; ParLe; assembler; configurable shared memory; graphical user interface; high-level parallel programming language; multiple processors interconnected; onchip networks; optimizing compiler; parallel computing learning set; parallel random access machines; statistical tools; systems on chip; Assembly; Computational modeling; Machine learning; Network-on-a-chip; Optimizing compilers; Parallel processing; Parallel programming; Phase change random access memory; Programming profession; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2005. Proceedings. 2005 International Symposium on
Conference_Location
Tampere
Print_ISBN
0-7803-9294-9
Type
conf
DOI
10.1109/ISSOC.2005.1595652
Filename
1595652
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