Title :
An alternative method of generating tests for path delay faults using Ni-detection test sets
Author :
Takahashi, Hiroshi ; Saluja, Kewal K. ; Takamatsu, Yuzo
Author_Institution :
Ehime Univ., Matsuyama, Japan
Abstract :
In order to generate tests for path delay faults we propose an alternative method that does not generate a test for each path delay fault directly. The proposed method generates an n-propagation test-pair set by using an Ni-detection test set for single stuck-at faults. The n-propagation test-pair set is a set of vector pairs which contains n distinct vector pairs for every transition fault at a checkpoint (primary inputs and fanout branches in a circuit are called check points). We do not target the path delay faults for test generation, instead, the n-propagation test-pair set is generated for the transition (both rising and falling) faults of check points in the circuit, and simulated to determine their effectiveness for singly testable path delay faults and robust path delay faults. Results of experiments on the ISCAS´85 benchmark circuits show that the n-propagation test-pair sets obtained by our method are very effective in testing path delay faults.
Keywords :
circuit testing; combinational circuits; fault diagnosis; logic testing; ISCAS´85 benchmark circuits; Ni-detection test set; checkpoint; n-propagation test-pair set; path delay faults; single stuck-at faults; test generation; transition faults; vector pairs; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Delay effects; Digital circuits; Electrical fault detection; Fault detection; Robustness; Timing;
Conference_Titel :
Dependable Computing, 2002. Proceedings. 2002 Pacific Rim International Symposium on
Print_ISBN :
0-7695-1852-4
DOI :
10.1109/PRDC.2002.1185647