DocumentCode
3278293
Title
Formal Modelling of Synchronous Hardware Components for System-on-Chip
Author
Westerlund, Tomi ; Plosila, Juha
Author_Institution
Turku Centre for Comput. Sci., Turku
fYear
2005
fDate
17-17 Nov. 2005
Firstpage
116
Lastpage
119
Abstract
In this paper we present aspects of synchronous hardware component design in a formal framework of timed action systems. Timed action systems is an extension of the action systems formalism that has been applied to the area of asynchronous and synchronous hardware design. We define synchronous operation of timed action systems and how timing characteristics of these systems are defined. Furthermore, we present time constraints that are used to confirm the tenability of timing during the development of hardware components.
Keywords
Boolean functions; asynchronous circuits; logic design; system-on-chip; temporal logic; asynchronous hardware design; formal modelling; synchronous hardware component design; synchronous hardware design; system-on-chip; timed action system; Command languages; Computer science; Concurrent computing; Hardware; Logic design; Signal processing; Software systems; System-on-a-chip; Time factors; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2005. Proceedings. 2005 International Symposium on
Conference_Location
Tampere
Print_ISBN
0-7803-9294-9
Type
conf
DOI
10.1109/ISSOC.2005.1595658
Filename
1595658
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