A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines

We propose a high-resolution 8-bit time-to-digital converter that uses two-level fractional difference conversion to reduce area and power consumption. Two delay-locked loops stabilize the propagation delay in the upper and lower buffer chains of the Vernier delay line that is used to make the measurement. In a transistor-level simulation using 0.35 ¿m technology, this architecture achieves a resolution of 24 ps with a 22 ps single-shot accuracy. The maximum sampling rate exceeds 5MS/s and the total power consumption is 8.81 mW.