Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator

In this paper the experimental validation along with mixed system integration of a novel, modified double scroll chaotic attractor circuit, employed as a true random binary generator (TRBG) is presented. The double scroll attractor is modeled on Chua´s circuit for nonlinear operation leading to double scroll chaotic behavior. The output from the chaotic circuit which is a correlated binary sequence is scrambled with a pseudo random binary sequence generator (PRBSG) topology to yield a true random binary source for key stream generation. The modified chaotic circuit has been implemented on printed circuit board (PCB) along with a field programmable gate array (FPGA) for true random bits generation. The randomness attributes of the hardware generator construction, using the PRBSG de-correlator were successfully tested by the well known NIST Test Suite and Diehard Test set for statistical validation. Output binary streams from the proposed modified generator were examined for randomness using both Test Suites with all tests successfully passed for both experimental chaotic circuit and PSpice simulation model which was used as a yardstick for statistical attributes. The hardware implementation of proposed TRBG has been constructed as a combination of chaotic generator analog circuitry on PCB and PRBSG digital operation leading to binary digit generation in FPGA. This TRSG system could be easily implemented as a complete hardware integrated cryptographic module for usage in mobile communication platform applications. A physical TRBG has been constructed on the basis of the proposed PRBSG modification with all statistical tests successfully passed.