Efficiency of Leakage Reduction Techniques on Different Static Logic Styles for Embedded Portable Applications with High Standby to Active Time Ratio

Leakage power is emerging as a major portion of the total power consumption in battery operated embedded systems. Thus, the designers face critical challenges in choosing the best circuit topologies with the appropriate leakage reduction technique in order to optimally balance the power and performance. This paper evaluates and compares the different static logic styles, with dual-threshold voltage and power gating techniques to attain low power and high performance VLSI systems in terms of power delay product and standby leakage power. A PMOS header for power gating with and without gated input schemes are evaluated. The simulations are carried out using a 180nm dual threshold mixed mode process technology.