Optimal system-level synthesis of digital systems for real-time applications

For the design of a digital system for real-time applications, it is necessary to get early and proper estimates of the timing constraints. These are normally obtained by the designer by synthesis on the system level. On this level, it is decided which part of an algorithm is implemented by application-specific hardware and which by software, performed by standard processors. Hardware resources are modeled without detailed functionality and the software utilizes these resources. Partitioning at the system level means determining a heterogeneous multiprocessor system and mapping tasks onto the system components. In this paper, we describe our system-level synthesis tool which supports the development of devices that need a digital system to perform tasks in real time (based on a formal model). The efficiency of the tool, which has been fully implemented and tested, is demonstrated using large practical examples