An improved register-transfer level functional partitioning approach for testability

This paper presents an improved register-transfer level functional partitioning approach for testability. Based on the earlier work (Kuchcinski and Peng (1994), the proposed method identifies the hard-to-test points initially based on data path testability and control state reachability. These points will be made directly accessible by DFT techniques. Then the actual partitioning procedure is performed by a quantitative clustering algorithm which clusters directly interconnected components based on a new proposed global testability of data path and global state reachability of control part. After each clustering step, we use a new estimation method which is based partially on explicit re-calculation and partially on gradient techniques for incremental testability and state reachability analysis to update the test property of the circuit. This process will be iterated until the design is partitioned into several disjoint subcircuits and each of them can be tested independently. The control part is then modified to control the circuit in normal and test mode accordingly. Therefore, test quality is improved by independent test generation and application for every partition by combing the effect of data path with control part. Experimental results show the advantages of the proposed algorithm compared with other conventional approaches