How faults can be simulated in self-testable VLSI digital circuits?

Computer based simulation of self testable VLSI digital circuits is a time consuming process. This is why new methods are still being developed to optimise the simulation process and to reduce its duration. The paper presents a new method of fault simulation, intended for self testable digital circuits. In this method, fault masking performed by an in-circuit tester is estimated, based on only the signature itself which is stored in compressor. It is not necessary to carry out a time consuming analysis of the digital circuit´s responses and compare them with stored model responses. Based on performed simulations, an observation was made that the developed method brings a substantial reduction of the duration of fault simulation processes performed for self testable digital circuits. It means the research laboratory needs considerably less time to verify the projects carried out on digital circuits