• DocumentCode
    327872
  • Title

    An useful micropipeline architecture to implement DSP algorithms

  • Author

    Choy, Chiu-Sing ; Pang, Tin-chak ; Povazaniec, J. ; Chan, Cheong-Fat

  • Author_Institution
    Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
  • Volume
    1
  • fYear
    1998
  • fDate
    25-27 Aug 1998
  • Firstpage
    212
  • Abstract
    The paper describes an asynchronous architecture to implement DSP algorithms using the micropipeline technique. The micropipeline technique is already quite popular in the asynchronous community due to its compatibility with the conventional logic. However, there is currently little guidance on how to use micropipeline for more complex designs. The architecture proposed will meet this need. The architecture is scalable to trade off between size and speed, and has automation potential
  • Keywords
    pipeline processing; reconfigurable architectures; signal processing; DSP algorithms; asynchronous architecture; automation; micropipeline architecture; scalable architecture; Delay effects; Digital signal processing; Flip-flops; Latches; Logic circuits; Logic design; Pipelines; Signal processing; Signal processing algorithms; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Euromicro Conference, 1998. Proceedings. 24th
  • Conference_Location
    Vasteras
  • ISSN
    1089-6503
  • Print_ISBN
    0-8186-8646-4
  • Type

    conf

  • DOI
    10.1109/EURMIC.1998.711802
  • Filename
    711802
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=327872