Logic process merging for conservative parallel simulation of logic circuits

Parallel simulation of digital logic circuits is a classic problem of parallel computing by featuring irregular, fine-grained parallelism. In the context of simulating digital IC design, the granularity of Logic Process (LP), which is the basic unit of parallel execution, is generally too small when compared to the scheduling and synchronization overhead of multi-core processors. In addition, the irregular communication pattern among different LPs makes it difficult to predict and optimize the inter-processor communication traffic. We propose a LP merging algorithm to address the above problems. The proposed algorithm coarsens the internal structure of input circuits to minimize communication and other overhead. At the same time, our algorithm preserves the inherent concurrency of the simulation. We elaborate the unique set of constraint for LP merging and the corresponding solutions. Experiments on real-world IP cores show that our LP merging algorithm results in a 20% reduction in the number of communication channels, the overall performance is boosted by 30% and the concurrency is maintained at a sufficient level.