On the design complexity of the issue logic of superscalar machines

Investigates the complexity of superscalar decode/issue logic-assuming primitive gates. We show, assuming that the issuing is performed on the basis of opcodes, that the complexity of checking data dependencies is O(k³) gates and O(log k) gate delay, k being the issue width, when assuming infinite resources and in-order issuing. In assuming out-of-order issuing, the complexities are O(2^k) gates and O(log k) gate delay, and, for out-of-order issuing with renaming, O(2^k) gates and O(k) gate delay. When the resources are restricted, we show that the complexity is O(n^k) gates and O(k² log n) delay, n being the cardinality of the instruction set. Finally, by assuming that the issuing is performed using grouping of instructions rather than an opcode-specific description, the complexity is O(m^k) gates and O(k² log m) delay, where m is the number of instruction groups