Title :
A transistor-level test strategy for C/sup 2/MOS MOUSETRAP asynchronous pipelines
Author :
Shi, Feng ; Makris, Yiorgos
Author_Institution :
Dept. of Electr. Eng., Yale Univ., New Haven, CT
Abstract :
We discuss a transistor-level test methodology for C2MOS asynchronous pipelines. Unlike their static CMOS counterparts, wherein testing for stuck-at faults and compliance to a few timing constraints typically suffices, dynamic asynchronous pipelines present new challenges which require more elaborate test solutions. More specifically, many gate-level input/output stuck-at faults of a static pipeline style translate into transistor-level stuck-open/stuck-short faults in the dynamic C2MOS version. Therefore, test methods for transistor-level faults are required for dynamic asynchronous pipelines. To this end, we propose a methodology for testing both gate-level stuck-at faults and transistor-level stuck-open/stuck-short faults in C2MOS pipelines. The proposed method does not employ additional hardware and is capable of detecting both gate-level and transistor-level faults, as we demonstrate on the C2MOS version of MOUSETRAP
Keywords :
CMOS logic circuits; asynchronous circuits; fault diagnosis; integrated circuit testing; logic testing; C2MOS asynchronous pipelines; MOUSETRAP asynchronous pipelines; dynamic asynchronous pipelines; stuck-at faults; transistor-level faults; transistor-level stuck-open faults; transistor-level stuck-short faults; transistor-level test strategy; CMOS logic circuits; Delay; Fault detection; Hardware; Logic design; Logic testing; Pipelines; Robustness; Test pattern generators; Timing;
Conference_Titel :
Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium on
Conference_Location :
Grenoble
Print_ISBN :
0-7695-2498-2
DOI :
10.1109/ASYNC.2006.7
