Title :
5.3 GHz 1.6 dB NF CMOS low noise amplifier using 0.11 μm technology
Author :
Satou, Hiroyuki ; Yamazaki, Hiroshi ; Kobayashi, Kazuhiko ; Mori, Toshihiko ; Watanabe, Yuu
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
We fabricated a low noise amplifier (LNA) for a 5 GHz WLAN with a supply voltage of 1.2 V using 0.11 μm CMOS technology. Low voltage design is crucial for an analog circuit to use the scaled digital CMOS. Employing the cascode amplifier configuration, we have shown that the LNA has a wide operating margin even at the supply voltage of 1.2 V. The measured LNA revealed an NF of 1.6 dB, a power consumption of 12.5 mW and 8.2 dBm of OIP3 at 5.3 GHz with a supply voltage of 1.2 V.
Keywords :
CMOS analogue integrated circuits; MMIC amplifiers; integrated circuit design; integrated circuit noise; power consumption; wireless LAN; 0.11 micron; 1.2 V; 1.6 dB; 12.5 mW; 5.3 GHz; CMOS low noise amplifier; LNA; OIP3; WLAN; analog circuit; analog circuit design; cascode amplifier; noise figure; power consumption; scaled digital CMOS; third order output intercept point; Analog circuits; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS technology; Circuit noise; Low voltage; Low-noise amplifiers; Noise measurement; Power amplifiers; Wireless LAN;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE
Print_ISBN :
0-7803-8333-8
DOI :
10.1109/RFIC.2004.1320541
