• DocumentCode
    3279346
  • Title

    Fine pitch copper wire bond process development for dual damascene Cu metallized chips

  • Author

    Sivakumar, Mohandass ; Kripesh, Vaidyanathan ; Loon Aik Lim ; Kumar, Madhu

  • Author_Institution
    Inst. of Microelectron., Bulgaria
  • fYear
    2002
  • fDate
    10-12 Dec. 2002
  • Firstpage
    350
  • Lastpage
    355
  • Abstract
    With the improvements in integrated circuit (IC) features, it becomes necessary to make a transition to a low resistive interconnect material. Copper (Cu) is preferred as an alternate interconnect material for high performance devices. The objective of the current research work is to develop a reliable fine pitch Cu wire bonding on a Cu metallized chip. Capillary design, Free Air Ball (FAB) study and process optimization are important for realizing a reliable Cu/Cu wirebond. Dual damascene Cu metallized test chip has been designed and fabricated. A cleaning process is developed and wire bonding process optimization has been carried out. Surface analysis by Auger electron spectroscopy (AES) and ball shear tests indicate unambiguously that the cleaning process has significant influence on the removal of Cu oxide and other contamination. With the new cleaning process and wire bond optimisation, a reliable Cu/Cu wire bond process is developed. The details of cleaning process and wire bond techniques are discussed in this paper.
  • Keywords
    Auger electron spectra; copper; fine-pitch technology; integrated circuit interconnections; integrated circuit metallisation; lead bonding; optimisation; surface cleaning; surface contamination; AES; Auger electron spectroscopy; Cu; capillary design; cleaning process; dual damascene Cu metallized chips; fine pitch Cu wire bond process development; free air ball; integrated circuits; low resistive interconnect material; process optimization; reliable Cu/Cu wirebond; reliable fine pitch wire bonding; surface analysis; wire bonding process optimization; Bonding processes; Cleaning; Copper; Design optimization; Integrated circuit interconnections; Integrated circuit reliability; Metallization; Surface contamination; Testing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2002. 4th
  • Print_ISBN
    0-7803-7435-5
  • Type

    conf

  • DOI
    10.1109/EPTC.2002.1185696
  • Filename
    1185696