Design and verification of an embedded microprocessor

Advances in VLSI technologies are enabling the construction of entire systems on a chip. A major challenge in the design of such systems is design verification. This paper presents the design and verification process used to develop Euphony. Euphony is an inexpensive low power system on a chip which contains: a RISC processor with DSP functions, a complex memory and device controller, two ATM network interfaces, architectural support for AAL5 SAR processing, a five channel DMA controller, and a serial port that can interface to wide variety of audio devices. Euphony was developed jointly by AT&T and LSI Logic. AT&T developed the architecture while LSI Logic performed the implementation using LSI Logic´s LCB500K 0.5 micron drawn cell-based ASIC processes. Both companies were heavily involved in design verification