Verifiable Embedded Real-Time Application Framework

Author

Hsiung, Pao-Ann ; Su, Feng-Shi ; Gao, Chuen-Hau ; Cheng, Shu-Yu ; Chang, Yu-Ming

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan

fYear

2001

fDate

2001

Firstpage

109

Lastpage

110

Abstract

A new application framework called Verifiable Embedded Real-Time Application Framework (VERTAF) is proposed for embedded real time application development, with the aim of reducing design errors and increasing design productivity. VERTAF is an integration of three technologies: object oriented, software component, and formal verification. It consists of five software components: Implanter, Modeler, Scheduler, Verifier, and Generator. Experiences of using VERTAF show a significant increase in design productivity through design reuse, and a significant decrease in design time and effort through design verification

Keywords

embedded systems; object-oriented programming; program verification; scheduling; software reusability; Generator; Implanter; Modeler; Scheduler; VERTAF; Verifiable Embedded Real-Time Application Framework; Verifier; design errors; design productivity; design reuse; design time; design verification; embedded real time application development; formal verification; object oriented; software component; software components; Application software; Design engineering; Embedded software; Formal verification; Job shop scheduling; Object oriented modeling; Process design; Productivity; Real time systems; Software design;

fLanguage

English

Publisher

ieee

Conference_Titel

Real-Time Technology and Applications Symposium, 2001. Proceedings. Seventh IEEE

Conference_Location

Taipei

ISSN

1080-1812

Print_ISBN

0-7695-1134-1

Type

conf

DOI

10.1109/RTTAS.2001.936258

Filename

936258