Title :
Delta-I modeling approximation for single chip modules
Author :
Katopis, G. ; Singh, Bawa ; Becker, W. ; Smith, H.
Author_Institution :
IBM Corp., Poughkeepsie, NY
Abstract :
In this paper the impact of the inductance path on the power plane of a representative single chip module for cost performance machines is quantified via loop inductance comparison and Delta-I noise simulations. In addition the impact of the inclusion of the via to pin mutual is investigated. Finally, a simplified model based on two dimensional analysis of the via and pin structure is compared with the most accurate analysis of this structure and it is shown that the error in loop inductance is only 10%, while the error in Delta-I peak noise is 2%
Keywords :
approximation theory; inductance; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; Delta-I modeling approximation; Delta-I noise simulation; SCM package; inductance path; loop inductance comparison; pin structure; power plane; single chip modules; two dimensional analysis; via structure; via to pin mutual;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1996., IEEE 5th Topical Meeting
Conference_Location :
Napa, CA
Print_ISBN :
0-7803-3514-7
DOI :
10.1109/EPEP.1996.564800
