Post CMOS integration of high aspect ratio SOI MEMS devices

A post CMOS fabrication process for integrating high aspect ratio MEMS devices with signal processing circuitry on SOI wafers is presented. The integrated SOI MEMS devices are attractive for better system performance and lower packaging cost. The interface circuitry on SOI wafer is fabricated in CMOS foundry and the MEMS device is processed in National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, China. In the integrated system, MEMS structure and the substrate of interface circuitry is electrically isolated by trenches and mechanically connected by the handle layer of the SOI wafer. Silicon dioxide bridges are used to support the wires that cross the trenches and transmit signals. To decrease the complexity of the process, the metal layer of the IC fabrication process serves as the etching mask of the high aspect ratio dry etching. The characteristics of the transistors are measured before and after the MEMS fabrication process and comparison between the measurement results demonstrate the feasibility of the process.