DocumentCode
3280831
Title
Development of TSV simulator: FASTsv
Author
Zhu, Fuyun ; Wang, Chen ; Yu, Min ; Zhao, Xin ; Jin, Yufeng ; Zhang, Haixia
Author_Institution
Nat. Key Lab. of Nano/Micro Fabrication Technol., Peking Univ., Beijing, China
fYear
2011
fDate
20-23 Feb. 2011
Firstpage
217
Lastpage
220
Abstract
The increasing need for functionality and portability in consumer electronics is pushing the microelectronics industry to develop more effective interconnection techniques. This has resulted in the birth of 3D stacking of chips, which is achieved by the use of TSV (Through-Silicon-Via) technology. This paper puts forward a TSV simulator, FASTsv (Fast and Accurate Simulator of TSV: FASTsv). The key technologies in TSV process include DRIE (deep reactive ion etching) and PECVD (plasma-enhanced chemical vapor deposition) processes. Based on experimental results and theoretical analysis, the modeling of DRIE and PECVD processes are developed. Experimental tests are performed to verify the TSV simulator. The simulation results agree with experimental results very well.
Keywords
chemical vapour deposition; integrated circuit interconnections; sputter etching; 3D stacking; FASTsv; TSV simulator; consumer electronics; deep reactive ion etching; interconnection techniques; microelectronics industry; plasma-enhanced chemical vapor deposition; through-silicon-via; Data models; Etching; Mathematical model; Polymers; Silicon; Sulfur hexafluoride; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Nano/Micro Engineered and Molecular Systems (NEMS), 2011 IEEE International Conference on
Conference_Location
Kaohsiung
Print_ISBN
978-1-61284-775-7
Type
conf
DOI
10.1109/NEMS.2011.6017333
Filename
6017333
Link To Document