DocumentCode
3280869
Title
Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process
Author
Chawla, J.S. ; Chebiam, Ramanan ; Akolkar, R. ; Allen, G. ; Carver, Colin T. ; Clarke, James S. ; Gstrein, F. ; Harmes, Michael ; Indukuri, Tejaswi ; Jezewski, Christopher ; Krist, Brian ; Lang, Helmut ; Myers, Amanda ; Schenker, Richard ; Singh, Kiran Jo
Author_Institution
Components Res., Intel Corp., Hillsboro, OR, USA
fYear
2013
fDate
13-15 June 2013
Firstpage
1
Lastpage
3
Abstract
A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.
Keywords
copper; dielectric materials; integrated circuit interconnections; lithography; Cu; ILD; copper fill; electrical measurement; half-pitch copper ultralow-k interconnect process; lithography; pattern transfer optimization; size 12 nm; size 193 nm; ultralow-k interlayer dielectric; Copper; Electrical resistance measurement; Lithography; Metallization; Resistance; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference (IITC), 2013 IEEE International
Conference_Location
Kyoto
Print_ISBN
978-1-4799-0438-9
Type
conf
DOI
10.1109/IITC.2013.6615593
Filename
6615593
Link To Document