System-level analysis for 3D interconnection networks

Author

Chenyun Pan ; Naeemi, Azad

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2013

fDate

13-15 June 2013

Firstpage

1

Lastpage

3

Abstract

This paper provides a fast and efficient approach to analyze and compare systems implemented with through-silicon via (TSV) and monolithic inter-tier via (MIV) 3D integration technologies based on compact models for cycle-per-instruction, memory throughput, and multi-level interconnect networks. Additionally, the impact of via diameter and capacitance on the overall system throughput has been quantified. It is demonstrated that for the same die area and thermal constraint, an MIV-based processor offers over 25% improvement in computational throughput as compared with its 2D counterpart.

Keywords

capacitance; integrated circuit interconnections; three-dimensional integrated circuits; 3D interconnection networks; MIV-based processor; capacitance; cycle-per-instruction; memory throughput; monolithic intertier via 3D integration technology; multilevel interconnect networks; system-level analysis; through-silicon via 3D integration technology; via diameter; Capacitance; Clocks; Logic gates; Repeaters; Three-dimensional displays; Throughput; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2013 IEEE International

Conference_Location

Kyoto

Print_ISBN

978-1-4799-0438-9

Type

conf

DOI

10.1109/IITC.2013.6615597

Filename

6615597