VHDL modeling of an adaptive architecture for real-time image enhancement

The aim of this work is to design a real-time adaptive and reusable image enhancement architecture for video signals, based on a statistical processing of the video sequence. The VHDL hardware description language has been used in order to make possible a top-down design methodology. Generic design methodology has been followed by means of two features of the VHDL: global packages and generic pass. Image processing systems like this one require specific simulation tools in order to reduce the development time. A VHDL test bench has been designed specifically for image processing applications to facilitate the simulation process. It was necessary to define a new image file format with special characteristics for this purpose. A physical realization has been carried out on a FPGA to prove the validation of the design