Parallel encoder, decoder, detector, corrector for cyclic redundancy checking

Redesigning the linear feedback shift register so that syndrome calculations can be performed in one sweep allows for fast error control in high-speed computer networks. The resulting structure forms the basis of the PEDDC (parallel encoder, decoder, detector, corrector) which replaces the conventional SEDDC (serial encoder, decoder, detector, corrector) for generation and utilization of cyclic codes. The authors built a PEDDC to harness the advantages of syndrome calculations from information acquired in parallel. Its operation is examined and its performance is compared with a SEDDC. Possible variations on the PEDDC structure are given, and further speed enhancement techniques are considered