Title :
Rapid design of testable, high-performance/capacity associative memories
Author :
Miller, P.M. ; Hurson, A.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Pennsylvania State Univ., Univesity Park, PA, USA
Abstract :
VLSI technology has created the opportunity for designers to develop special-purpose application-specific architectures based on associative processing techniques. However the diversity of these applications creates a need for a generalized methodology to quickly produce high-capacity associative chips with different functionalities. The paper introduces such a scheme for designing special-purpose content-addressable memories (CAMs). An overall CAM organization suitable for most special-purpose associative chips is presented and the design, layout, and performance of its modular components is discussed. An example CAM is examined to show the performance and area efficiency of CAMs designed using the proposed scheme. The paper also introduces an improved, highly compact θ-search associative cell. Finally, the testing of CAMs using this organization is discussed
Keywords :
VLSI; application specific integrated circuits; circuit layout CAD; content-addressable storage; integrated circuit testing; integrated memory circuits; &thetas;-search associative cell; VLSI technology; application-specific architectures; area efficiency; associative memories; associative processing; layout; performance; special-purpose associative chips; special-purpose content-addressable memories; testing; Application software; Associative memory; CADCAM; Cams; Computer aided manufacturing; Logic; Random access memory; Read-write memory; Testing; Very large scale integration;
Conference_Titel :
Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-2087-0
DOI :
10.1109/SPDP.1990.143637