A family of bias circuits for high input swing CMOS operational amplifiers

A set of three circuits for biasing CMOS amplifiers with rail-to-rail input common-mode range is presented. By controlling the bias current levels, they avoid the large magnitude deviations inherent in these amplifiers with composite input pairs. The deviations are with regard to their value for input voltages in the mid-range between supplies. Thus, the optimization and compensation is facilitated, as well as an increase in the common-mode rejection ratio (CMRR) over 17 dB in comparison to the classical biasing schemes