Pipelined architecture for FPGA implementation of lifting-based DWT

Author

Wu, Zhigang ; Wang, Wei

Author_Institution

Coll. of Poly-Technol., Sichuan Normal Univ., Chengdu, China

fYear

2011

fDate

15-17 April 2011

Firstpage

1535

Lastpage

1538

Abstract

This paper presents a high speed 9/7 lifting 1D-DWT algorithm which is implementation on FPGA with multi-stage pipelining structure. Compared with the architecture which without multi-stage pipeline, the proposed architecture has higher operating frequency, the design raises operating frequency around 1.5 times more fast, at the expense of about 27% more hardware area. The hardware architecture is suitable for high speed implementation.

Keywords

discrete wavelet transforms; field programmable gate arrays; pipeline processing; 9/7 lifting 1D-DWT algorithm; FPGA; discrete wavelet transforms; field programmable gate arrays; pipelined architecture; Adders; Computer architecture; Discrete wavelet transforms; Image coding; Pipeline processing; Discrete wavelet transform (DWT); FPGA; lifting scheme; multi-stage pipelining;

fLanguage

English

Publisher

ieee

Conference_Titel

Electric Information and Control Engineering (ICEICE), 2011 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-8036-4

Type

conf

DOI

10.1109/ICEICE.2011.5777731

Filename

5777731

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3282786