DocumentCode
3283159
Title
Design of a novel domino XNOR gate for 32 nm-node CMOS technology
Author
Guo, Baozeng ; Ma, Tao ; Zhang, Yubo
Author_Institution
Coll. of Electron. & Informational Eng., Hebei Univ., Baoding, China
fYear
2011
fDate
15-17 April 2011
Firstpage
289
Lastpage
292
Abstract
A novel domino XNOR gate is designed, using techniques of pn mixed pull-down network and dual-threshold voltage. HSPICE simulation results prove that compared with the standard n-type domino XNOR gate the dynamic power of proposed design can be reduced by 43.9% and the minimum static power is reduced by 86.4%, while enhancing the AC noise immunity by 12.5%.
Keywords
CMOS logic circuits; SPICE; logic gates; network synthesis; AC noise immunity; CMOS technology; HSPICE simulation; domino XNOR gate; dual-threshold voltage; pn mixed pull-down network; size 32 nm; Inverters; Leakage current; Logic gates; Noise; Power demand; Threshold voltage; Transistors; Dynamic power; Leakage Current; Minimum static power; Noise immunity; XNOR Gate;
fLanguage
English
Publisher
ieee
Conference_Titel
Electric Information and Control Engineering (ICEICE), 2011 International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-8036-4
Type
conf
DOI
10.1109/ICEICE.2011.5777751
Filename
5777751
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