Lattice-Mismatch and CMOS

Author

Fitzgerald, E.A.

fYear

2005

fDate

7-9 Dec. 2005

Firstpage

127

Lastpage

128

Abstract

We show that increasing the lattice constant on which CMOS electronics is constructed allows for an increasing electron and hole mobility in the NMOS and PMOS devices, respectively. This trend began with strained Si, and we have shown in research devices that compressed Ge combined with tensile Si can create previously unattainable high mobility MOS with high inversion charge. We also show that by increasing the lattice on Si to Ge, III-V electron channels become feasible, as well as integrated III-V optoelectronics. The core technology in advancing this lattice constant roadmap is dislocation and interface defect control

Keywords

CMOS integrated circuits; III-V semiconductors; electron mobility; elemental semiconductors; germanium; hole mobility; lattice constants; silicon; CMOS electronics; Ge; III-V electron channels; III-V optoelectronics; NMOS devices; PMOS devices; Si; electron mobility; hole mobility; interface defect control; lattice constant; lattice mismatch; Capacitance-voltage characteristics; Capacitive sensors; Charge carrier processes; Electron mobility; Germanium silicon alloys; III-V semiconductor materials; Lattices; MOS devices; Silicon alloys; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2005 International

Conference_Location

Bethesda, MD

Print_ISBN

1-4244-0083-X

Type

conf

DOI

10.1109/ISDRS.2005.1596012

Filename

1596012