DocumentCode
3283371
Title
A systolic architecture for LMS adaptive filtering with minimal adaptation delay
Author
Ramanathan, S. ; Visvanathan, V.
Author_Institution
Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
fYear
1996
fDate
3-6 Jan 1996
Firstpage
286
Lastpage
289
Abstract
Existing systolic architectures for the LMS algorithm with delayed coefficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents a systolic architecture with minimal adaptation delay and input/output latency, thereby improving the convergence behaviour to near that of the original LMS algorithm. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the delayed LMS algorithm. With the use of carry-save arithmetic, the systolic folded pipelined architecture can support very high sampling rates, limited only by the delay of a full adder
Keywords
VLSI; adaptive filters; convergence of numerical methods; delays; digital filters; digital signal processing chips; least mean squares methods; pipeline processing; signal flow graphs; systolic arrays; LMS adaptive filtering; LMS algorithm; SFG representation; carry-save arithmetic; convergence behaviour; function preserving transformations; minimal adaptation delay; signal flow graph; systolic architecture; systolic folded pipelined architecture; Adaptive filters; Algorithm design and analysis; Arithmetic; Broadcasting; Convergence; Degradation; Delay; Flow graphs; Least squares approximation; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-8186-7228-5
Type
conf
DOI
10.1109/ICVD.1996.489612
Filename
489612
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