VLSI implementation of artificial neural network based digital multiplier and adder

Author

Ranade, Ranjeet ; Bhandari, Sanjay ; Chandorkar, A.N.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India

fYear

1996

fDate

3-6 Jan 1996

Firstpage

318

Lastpage

319

Abstract

This paper describes a technique to realize a novel digital multiplier using Artificial Neural Network (ANN). It proposes a generalized `Energy Function´ for multiplier and its hardware realization by combining conventional digital hardware with a neural network. The design of neurons, extended range active loads and the digital multiplier are described in this paper along with the simulation results

Keywords

CMOS digital integrated circuits; VLSI; adders; digital arithmetic; multiplying circuits; neural chips; parallel processing; ANN; VLSI implementation; adder; artificial neural network; digital multiplier; energy function; extended range active loads; Adders; Arithmetic; Artificial neural networks; Circuits; Hopfield neural networks; Linearity; Logic; Neural networks; Neurons; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1996. Proceedings., Ninth International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-8186-7228-5

Type

conf

DOI

10.1109/ICVD.1996.489620

Filename

489620

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3283508