Hardware-learning neural network LSI using a highly-functional transistor simulating neuron actions

Author

Ishii, Hiroshi ; Shibata, Tadashi ; Kosaka, Hideo ; Ohmi, Tadahiro

Author_Institution

Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan

Volume

1

fYear

1993

fDate

25-29 Oct. 1993

Firstpage

907

Abstract

This paper describes the architecture and the organization of a hardware-learning neural network LSI, in which a newly developed "brain-cell-like" transistor called neuron MOSFET (neuMOS or νMOS) is utilized not only in a neuron cell but also in a synapse cell. In order to implement learning capability on a chip, a new hardware-oriented backpropagation learning algorithm has been developed. The actions for self-learning based on this algorithm are also carried out by νMOS logic circuits.

Keywords

MOS logic circuits; MOSFET; backpropagation; large scale integration; neural chips; neural net architecture; unsupervised learning; LSI; architecture; backpropagation learning; hardware-learning neural network; logic circuits; neural chips; neuron MOSFET; neuron cell; self-learning; synapse cell; Backpropagation algorithms; Biological neural networks; Inverters; Large scale integration; Logic circuits; MOSFETs; Neural networks; Neurons; Power dissipation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on

Print_ISBN

0-7803-1421-2

Type

conf

DOI

10.1109/IJCNN.1993.714058

Filename

714058