DocumentCode
3283627
Title
Dual rail static CMOS architecture for wave pipelining
Author
Fernández, G. Enrique ; Sridhar, Ramalingam
Author_Institution
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
fYear
1996
fDate
3-6 Jan 1996
Firstpage
335
Lastpage
336
Abstract
Wave-pipelining is a special pipelining technique used in digital systems to achieve high throughput, with the use of gate capacitance as storage elements. An ideal system should have minimal delay variations amongst all paths. A dual-rail static CMOS (DRSCMOS) technique is presented for wave-pipelining. The availability of multi-functional basic building blocks and their low power consumption makes this an attractive approach
Keywords
CMOS logic circuits; capacitance; combinational circuits; delays; pipeline processing; timing; DRSCMOS; combinational logic block; delay variations; digital systems; dual rail static CMOS architecture; gate capacitance; multi-functional basic building blocks; power consumption; storage elements; throughput; wave pipelining; CMOS logic circuits; Capacitance; Clocks; Delay; Logic design; MOS devices; Pipeline processing; Rails; Throughput; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-8186-7228-5
Type
conf
DOI
10.1109/ICVD.1996.489628
Filename
489628
Link To Document